ANTONY AUSTIN

Engineer · Builder · Creator

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VLSI & Computer ArchitectureRTL, verification and Sky130A GDSII signoff complete — compiler and kernels ongoingFeatured

32-Bit Tiny GPU

A 32-bit SIMT GPU built from scratch in SystemVerilog: custom ISA, AXEL assembler, axelcc C-subset compiler, 391 cocotb tests, and a full RTL-to-GDSII run on SkyWater 130 nm with zero DRC violations.

March 2026 - Present
SystemVerilog /SIMT /GPU Architecture /ISA Design /OpenLane /Sky130 /Physical Design /cocotb /Compilers /Verilog /Python
32-Bit Tiny GPU

Project Overview

32-Bit Tiny GPU is a custom 32-bit SIMT GPU built from scratch in SystemVerilog — designed solo across every layer, from the instruction set to a manufacturable silicon layout. The design implements true SIMT execution: branch divergence is handled by a hardware warp stack with reconvergence, and a round-robin arbiter mediates memory access between warps. Around the core sit an MMIO matmul accelerator, a cycle-accurate execution trace logger, and a hardware kernel cycle counter. Software is a full stack of its own: AXEL, a C-library assembler, and axelcc, a C-subset compiler that emits kernels for the GPU's own ISA. Workloads are Q8 fixed-point neural networks, up to a chained 64-to-16-to-10 classifier running end to end on the RTL. The design has been taken all the way through OpenLane 2 to a signoff-clean GDSII on SkyWater Sky130A, and also targets the Sipeed Tang Nano 20K FPGA.

Objectives

  • Design a 30-instruction fixed-width 32-bit SIMT ISA with a 6-bit opcode field, spanning arithmetic, logic, shifts, memory, control flow, subroutine call and return, and an ML-oriented DOT4 extension
  • Implement the full RTL datapath in SystemVerilog — dispatcher, scheduler, fetcher, decoder, ALU, LSU, register file, program counter, memory controller, warp stack, DCR and core
  • Handle SIMT branch divergence properly, with a hardware warp stack and reconvergence rather than lockstep-only execution
  • Build a software stack on top: the AXEL assembler and axelcc, a C-subset compiler targeting the GPU's ISA
  • Verify every module under cocotb rather than inspecting waveforms by hand
  • Run Q8 fixed-point neural network workloads on the simulated hardware, up to a chained multi-layer classifier
  • Take the design through an open-source RTL-to-GDSII flow to a DRC- and LVS-clean layout

Project Gallery

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